Traditionally, high temperature C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a substrate. Conventionally, the C4 bumps are made from leaded solder, as it has superior properties. For example, lead is known to mitigate thermal coefficient (TCE) mismatch between the package and the substrate (i.e., organic laminate). Accordingly, stresses imposed during the cooling cycle were mitigated by the lead C4 bumps, thus preventing wiring layers from delaminating or other damage from occurring to the chip or the substrate.
However, lead-free requirements are now being imposed by many countries forcing manufacturers to implement new ways to produce chip to substrate joints. For example, solder interconnects consisting of tin/copper, tin/silver and SAC alloys have been used as a replacement for leaded solder interconnects. However, low ductility of such tin rich solders vs. leaded solders (Young's modulus of Sn 50 GPA vs. Pb 16 GPA) causes a transfer of stress through the C4 joint during assembly process (e.g., during a cooling cycle after reflow). Cracks in chip metallurgy under C4 bumps have been observed, which are named “white bumps” due to their appearance in sonoscan type inspection processes.
More specifically, in practice, the organic laminate has a TCE of about 18 to 20; whereas, the TCE of the chip is about 2. During the soldering process, e.g., reflow oven, the temperatures can range from about 250° C. to 260° C. This high temperature expands the organic laminate more than the chip due to the differences in the TCE. As the package (laminate, solder and chip) begins to cool, the solder begins to solidify (e.g., at about 180° C.) and the laminate begins to shrink as the chip remains substantially the same size. As the solder is robust and exceeds the strength of the chip, tensile stresses begin to delaminate structures on the chip. For example, it has been found that the wiring layers of the chip have delaminated due to the tensile stresses originating from the laminate and imposed from the solder bump to the chip. This process and resulting delamination is shown, for example, in FIG. 1.
However, currently there is no known tool to predict the location of white bumps and hence potential failure points of the chip during the packaging process. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.